JOINT PLENARY SPEAKERS

Joël Hartmann

Executive Vice President

Digital & Smart Power Technology and Digital Front-End Manufacturing

STMicroelectronics, France

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Artificial Intelligence: Why Moving it to the Edge?

This keynote is describing the evolution of Artificial Intelligence (AI) adoption to the Edge for maximizing Data processing at the User experience level to treat as much as possible data analysis without saturating Internet traffic and Cloud data centers. Evolution of Neural Network (NN) computing through progressive usage of In Memory Computing (IMC) is also described. A few examples of Artificial Intelligence at the Edge are also commented. We then describe how at ST, we address competitive solutions for Edge AI thanks to differentiated FD-SOI CMOS technology, Phase Change Memory (PCM) embedded memory integration and advanced NN and IMC design solutions.

 

Joël Hartmann is Executive Vice President of STMicroelectronics, Digital & Smart Power Technology and Digital Front-End Manufacturing, and has held this position since February 2012. He manages ST’s manufacturing operations in Crolles and Rousset, France, Technology and Design Platforms for the Company’s digital products. In December 2018, Hartmann’s mandate was expanded with ST’s Smart Power Technology R&D operations in Agrate, Italy. From 1979 to 2000, Hartmann worked at CEA-Leti, France-based applied-research center. In 2000, he joined STMicroelectronics as Director of the Crolles2 Alliance, the semiconductor manufacturing R&D initiative of STMicroelectronics, NXP, and Freescale Semiconductor. In 2008, Hartmann was promoted to Group Vice President and Director of Advanced CMOS Logic & Derivative Technologies. From 2010 to 2012, he had additional responsibilities as a co-leader of the Semiconductor Research and Development Center in Fishkill, NY, within the IBM ISDA Technology Alliance for advanced CMOS process development. Hartmann is a Member of the IEEE Electron Device Society. In 2017, he became a member of the French “Académie des Technologies” and received the European SEMI Award in 2019. Hartmann has filed 15 patents on semiconductor technology and devices and authored 10 publications in this field to date. Joël Hartmann was born in Toulon, France, in 1955. He graduated from the Ecole Nationale Supérieure de Physique de Grenoble with a degree in Physics.

Jean-René Léquepeys
Deputy Director, Chief Technology Officer

CEA-Leti, France

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Overcoming the Data Deluge Challenges with Greener Electronics

The purpose of this paper is to propose scientific and technical directions to reach global data and power sobriety while preserving computational efficiency. We present nine opportunities to lower the power consumption of computing units. A growth factor of 100 to 1000 in energy efficiency is achievable in the next 10 years if we take full advantage of all the potential improvements, working simultaneously at all five levels of the technological ecosystem (process steps, circuits, architecture, software and algorithms).

 

Jean-René Lèquepeys was named CEA-Leti's Vice-President and Director of Programs in January 2019, following more than 30 years of scientific and managerial leadership at both CEA and CEA-Leti. He joined CEA in 1985 in the detection and intrusion-detection laboratory in CEA's central security department and was promoted to lab manager in 1987. He joined CEA-Leti in 1993 as an R&D engineer specializing in image processing and also worked on the institute's telecom projects. He was named head of deployment of the Telecom, Communicating Objects and Smart Card programs in 1999 and was promoted to head of the Circuit Design Department of CEA-Leti in 2005. In that role, Jean-René created a research center in Gardanne (France), pioneering secured electronic components, in partnership with School of Mines of Saint-Etienne (France). In 2010, he started a new department specializing in electronic architectures, integrated circuit design and embedded software, bringing together CEA-Leti and CEA-List researchers. He also helped launch CEA-Leti's Silicon Components Division in 2011 and was named head of the division in 2017. Jean-René returned to the Electronic Architectures, Integrated Circuit Design and Embedded Software Department in 2018 before taking his current position.

Jean-René graduated from Supélec (1983) and taught physics for two years in Ouarzazate, Morocco. In 2000, he won the "Grand Prix de l'électronique Général Ferrié" for his work in telecommunications. He holds approximately 15 patents in that field.

Jan M. Rabaey
Professor Emeritus, Professor in the Graduate School
Electrical Engineering and Computer Sciences 
University of California, Berkeley, USA

 

Architecting the Human Intranet

Equipping us humans with the necessary tools to interact with, survive, and prosper in a rapidly changing world may require us to intimately adopt some of the same technologies that are causing some of these changes. Various wearable devices have been or are being developed to do just that. To be effective, functionality cannot be centralized and needs to be distributed to capture the right information at the right place. This requires a human intranet, a platform that allows multiple distributed input/output and information processing functions to coalesce and form a single application. How to effectively do so in light of the many challenges from an efficiency, usability, and effectiveness perspective is the focus of this paper.

 

Jan M. Rabaey holds the Donald O. Pederson Distinguished Professorship at the University of California at Berkeley. He is a founding director of the Berkeley Wireless Research Center (BWRC) and the Berkeley Ubiquitous SwarmLab, and has been the the Electrical Engineering Division Chair at Berkeley twice.

Prof. Rabaey has made high-impact contributions to a number of fields, including advanced wireless systems, low power integrated circuits, sensor networks, and ubiquitous computing. His current interests include the conception of the next-generation integrated wireless systems over a broad range of applications, as well as exploring the interaction between the cyber and the biological world.

He is the recipient of major awards, amongst which the IEEE Mac Van Valkenburg Award, the European Design Automation Association (EDAA) Lifetime Achievement award, and the Semiconductor Industry Association (SIA) University Researcher Award. He is an IEEE Fellow, a member of the Royal Flemish Academy of Sciences and Arts of Belgium, and has received honoray doctorates from Lund (Sweden), Antwerp (Belgium) and Tampere (Finland). He has been involved in a broad variety of start-up ventures.

 

ESSCIRC KEYNOTE SPEAKERS

Maurits Ortmanns
Professor

Institute of Microelectronics

Ulm University, Germany
 

Wideband and Low-Power Delta-Sigma ADCs: State of the Art, Trends and Implementation Examples

Continuous-time Delta-Sigma (∆Σ) ADCs have obtained a dominant position for the digitization in wireless receivers. With steadily improved theoretical understanding, architectural innovations and excellent circuit designs, they have achieved bandwidths of hundreds of MHz, while showing high resolution with highly competetive power efficiency. Moreover, due to their filtering properties, CT ∆Σ modulators are highly attractive for hostile receiver environments. In this review, the background and recent architectural and circuit innovations will be highlighted, including an exceeding number of hybrid designs, which improved both the application scenario as well as the power efficiency of this class of ADC. State-of-the-art examples will be illustrated and open research topics discussed.

 

Prof. Dr.-Ing. Maurits Ortmanns received the Dipl.-Ing. in electrical engineering from the Saarland University, Saarbruecken, Germany, in 1999 and the Dr.-Ing.degree from the Albert-Ludwigs-University, Freiburg, Germany, in 2004, both with highest honors.

In 1997 and 1998, he was with the Research Center Karlsruhe, Germany, and with EXAR, Inc., Fremont, CA, as an engineering intern working in the field of Microsensors. In 1999, he joined the Institute of Microelectronics at the Saarland University, where he was working as are search assistant. In 2001, he moved to the Institute of Microsystem Technology, Albert-Ludwigs-University, where he was working toward the Ph.D. degree in the field of continuous-time sigma-delta modulator design until 2004.

From 2004 - 2005, he has been with sci-worx GmbH, Hannover, Germany, where he was working in the field of mixed-signal and analog circuits for biomedical implants, low-voltage, low-power applications, and high-speed circuits. In the beginning of 2006, Dr. Ortmanns joined the HSG-IMIT, Villingen-Schwenningen, Germany, and was additionally a guest lecturer at the University of Freiburg, Germany. In May 2006, he was appointed a Juniorprofessorship for Integrated Interface Circuits at the Institute for Microsystems Engineering in Freiburg.

Since May 2008, Prof. Ortmanns is full professor at at the Faculty of Electrical Engineering and Computer Science at the University of Ulm, where he heads the Institute of Microelectronics.

Prof. Ortmanns received the VDI and the VDE award for his Master studies in electrical engineering from the Saarland University in 1999, the ITG Publication Award 2015, and the Best Student Paper Awards at MWSCAS 2009 and at SampTA 2011. He also received the faculty's teaching award 2012 and 2015.

He served as program committee member of the European Solid State Circuits Conference (ESSCirC), the Design Automation and Test Conference (DATE) and the European Conference on Circuit Theory and Design (ECCTD),  Associate Editor of the IEEE Transactions of Circuits and Systems I, Guest Editor of the IEEE Journal Solid State Circuits, and is currently Associate Editor of the IEEE Transactions of Circuits and Systems II. Prof. Ortmanns is a Technical Program Committee member of the IEEE International Solid-State Circuits Conference (ISSCC) since 2012,  an Executive Committee member of ISSCC since 2013 and European TPC Chair of ISSCC 2015. He holds a dozen patents, is author of the book “Continuous-Time Sigma-Delta A/D Conversion”, and published several other book chapters and more than 190 IEEE journal and conference papers.

 
Carlo Samori
Professor
Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB)
Politecnico di Milano, Italy

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Digital PLLs: the Modern Timing Reference for Radar and Communication Systems

Digital PLLs are nowadays recognized as a viable approach for the design of high-performance frequency synthesizers in scaled CMOS technologies. Latest implementations allow achieving at low power both state-of-the-art rms jitter, between 50fs and 100fs, and highly linear fast frequency modulation capability, thus enabling both high-efficiency communications systems and radar applications in CMOS. This paper will briefly trace the path from the (re-)discover of this approach to the more recent solutions, discussing the main characteristics of key building blocks and their limitations such as the non-linearities, and the noise, that still calls for a sound knowledge of analog design techniques.

 

Carlo Samori, IEEE Fellow, is Full Professor in the Master Degree in Electrical Engineering at Politecnico Milano, presently teaching the course “Mixed-signal circuits”. His research interests are in the field of analog/mixed signal and RF integrated circuits design, in scaled CMOS technologies (presently 65nm and 28 nm). The activity has been focused in particular in the area of the frequency synthesis: the design of low-noise oscillators, the design and analysis of new high-performance PLLs architectures and frequency modulators for wireless communications.

He is the co-author of about 130 peer reviewed international publications, and of the book “Integrated frequency synthesizers for wireless systems”, Cambridge University Press (2007), in addition to several books chapters.

From 1997 to 2002 he has been a consultant at Bell Labs, Murray Hill (NJ), he has also collaborated with several companies operating in the area of both semiconductors and communications: STMicroelectronics, Ericsson Lab Italy, Intel Labs (Hillsboro OR, USA), and Infineon Technologies.

He has been also involved in several research programs, both Italian and international.

For the IEEE he has held courses both at tutorial levels (ISSC tutorial and IEEE webminar) and more advanced (ISSC forum).

He has been a member of the Technical Program Committee (TPC) of the IEEE International Solid-State Circuits Conference (ISSCC) and of the TPC in the European Solid-State Circuits Conference (ESSCIRC). He has been Guest Editor of the IEEE Journal of Solid-State Circuits.

As IEEE Distinguished Lecturer he has given lectures at University of Texas Austin, University of Toronto, Georgia Institute of Technology, Princeton University.

He is an IEEE Fellow.

Ali Sheikholeslami
Professor
Electrical and Computer Engineering
University of Toronto, Canada

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The Power of Parallelism in Stochastic Search for Global Optimum

We explore the power of parallelism in a stochastic search for global optimum in high-dimensional optimization problems. This search, that often navigates a large solution space through a Markov-Chain Monte Carlo (MCMC) process, needs to make stochastic decisions at every step and needs to escape from local optima. Through parallelism, we are able to survey an entire neighborhood (all states with Hamming distance of 1) to make efficient moves, use multiple replicas at different temperatures, such as in parallel tempering, or deploy a population of replicas at the same temperature. Once combined, these methods of parallelism can yield 100x to 10,000x speedups.

 

Ali Sheikholeslami received the B.Sc. degree from Shiraz University, Shiraz, Iran, in 1990 and the M.A.Sc. and Ph.D. degrees from the University of Toronto, Toronto, ON, Canada, in 1994 and 1999, respectively, all in electrical and computer engineering. In 1999, he joined the Department of Electrical & Computer Engineering, University of Toronto, where he is currently a professor.  His research interests are in the areas of analog and digital integrated circuits, high-speed signaling, and VLSI memory design (including STT-MRAM). He spent his 2005-2006 research sabbatical with Fujitsu Labs of Japan and Fujitsu Labs of America. He is currently spending his 2012-2013 research sabbatical with Analog Devices in Toronto, Canada.

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